LTC4252A-1IMS#TRPBF【PDF 20/36 页】IC CNTRLR HOTSWAP NEGVOLT 10MSOP

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LTC4252-1/LTC4252-2

LTC4252A-1/LTC4252A-2

425212fe

For more information www.linear.com/LTC4252-1

Approximating a linear charging rate as I

DRN

drops from

DRN(MAX)

to zero, the I

DRN

component in Equation (3)

can be approximated with 0.5 " I

DRN(MAX)

. Rearranging

equation, TIMER capacitor C

is given by:

CL(CHARGE)

" 230礎+4"I

DRN(MAX)

(

)

(13)

Returning to Equation (3), the TIMER period is calcu-

lated and used in conjunction with V

SUPPLY(MAX)

and

SHORTCIRCUIT(MAX)

to check the SOA curves of a prospec-

tive MOSFET .

As a numerical design example, consider a 30W load,

which requires 1A input current at 36V . If V

SUPPLY(MAX)

= 72V and C

= 100礔 , R

= 1M? Equation (8) gives R

= 40m? Equation (13) gives C

= 441nF . To account for

errors in R

, C

, TIMER current (230礎), TIMER threshold

(4V), R

, DRAIN current multiplier and DRAIN voltage

clamp (V

DRNCL

), the calculated value should be multiplied

by 1.5, giving the nearest standard value of C

= 680nF .

If a short-circuit occurs, a current of up to 120mV/40m=?A

will flow in the MOSFET for 5.6ms as dictated by C

??80nF

in Equation (3). The MOSFET must be selected based on

this criterion. The IRF530S can handle 100V and 3A for

10ms and is safe to use in this application.

Computing the maximum soft-start capacitor value during

soft-start to a load short is complicated by the nonlinear

MOSFETs SOA characteristics and the R

response.

An overly conservative but simple approach begins with

the maximum circuit breaker current, given by:

CB(MAX)

(14)

where V

CB(MAX)

= 60mV (55mV for the LTC4252A).

From the SOA curves of a prospective MOSFET , determine

the time allowed, t

SOA(MAX)

. C

is given by:

SOA(MAX)

0.916"R

(15)

In the above example, 60mV/40m?gives 1.5A. t

SOA(MAX)

for the IRF530S is 40ms. From Equation (15), C

437nF . Actual board evaluation showed that C

= 100nF

was appropriate. The ratio (R

" C

) to t

CL(CHARGE)

a good gauge as a large ratio may result in the time-out

period expiring. This gauge is determined empirically with

board level evaluation.

SUMMARY OF DESIGN FLOW

To summarize the design flow, consider the application

shown in Figure 2 with the LTC4252A. It was designed

for 80W.

Calculate the maximum load current: 80W/43V = 1.86A;

allowing for 83% converter efficiency, I

IN(MAX)

= 2.2A.

Calculate R

: from Equation (8) R

= 20m?

Calculate I

SHORTCIRCUIT(MAX)

: from Equation (10)

SHORTCIRCUIT(MAX)

66mV

20m&

=3.3A

Select a MOSFET that can handle 3.3A at 71V: IRF530S.

Calculate C

: from Equation (13) C

= 322nF . Select

??80nF , which gives the circuit breaker time-out period

t? 5.6ms.

Consult MOSFET SOA curves: the IRF530S can handle 3.3A

at 100V for 8.2ms, so it is safe to use in this application.

Calculate C

: using Equations (14) and (15) select

??8nF .

FREQUENCY COMPENSATION

The LTC4252A typical frequency compensation network for

the analog current limit loop is a series R

(10? and C

connected to V

. Figure 7 depicts the relationship between

the compensation capacitor C

and the MOSFETs C

ISS

The line in Figure 7 is used to select a starting value for C

based upon the MOSFETs C

ISS

specification. Optimized

values for C

are shown for several popular MOSFETs.

Differences in the optimized value of C

versus the starting

value are small. Nevertheless, compensation values should

be verified by board level short-circuit testing.

applicaTions inForMaTion

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